I/O Systems - Example Buses

VMEbus

Principles

(See lecture)

Functional Structure

This structure consists of interface logic, four groups of lines called buses, and a collection of functional modules associated with them.

Data Transfer Bus

The data transfer bus consists of 32 data lines, 32 address lines, 6 address modifier lines, and 5 control lines. In addition to the master and slave, the functional modules of this bus also include the location monitor and the bus timer.

The master initiates data transfer bus cycles in order to transfer data with a slave module. The slave detects data transfer bus cycles initiated by a master, and when those cycles specify its participation, transfers data between itself and the master.

The location monitor monitors data transfers in order to detect accesses to the locations it has been assigned to watch. When an access occurs to one of these locations, the monitor can alert its processor by means of an interrupt. For example, if processor board A writes into a location of the global memory monitored by processor B's location monitor, processor B will be interrupted.

The bus timer measures how long each transfer takes, and termi­nates the bus cycle if it takes too long. It is useful when a master try to address a nonexistent memory location or slave module. The bus timer prevents the hanging of the bus.

The data transfer bus features nonmultiplexed address and data lines to maximize system performance when numerous single-transfers are executed (for example, instruction fetches). For these transfers, the pro­cessor sends an address and then reads or writes the data.

Priority Interrupt Bus

It consists of 7 interrupt request lines, -IRQ1 -IRQ7, one interrupt acknowledge line, -IACK, and an interrupt acknowledge daisy chain. Because there can be multiple CPUs and multiple devices, the request lines can be partitioned among more interrupt controllers, with each controller monitoring specific lines and being responsible for interrupting a specific CPU

The interrupt source generates an interrupt request. When its request is acknowledged by an interrupt handler, the interrupt source provides 1, 2, or 4 bytes of status or identification during the interrupt acknowledge cycle, which allows the interrupt handler to service the interrupt.

The interrupt acknowledge daisy-chain will be activated whenever an interrupt handler acknowledges a request. This daisy-chain ensures that only one interrupter responds with its status or identification when more than one has generated a request.

Arbitration Bus

The arbitration process allows the selection of a master or interrupt handler that is granted use of the data transfer bus. The arbitration bus consists of 4 bus request lines, -BR0 -BR3, 4 daisy-chained bus grant lines, -BG0IN -BG3IN, and two other lines called Bus Busy (-BBSY) and Bus Clear (-BCLR

There is a bus requester which resides on the same board as a master or interrupt handler. After the request, the requester waits for the arbiter to acknowledge the request, then it takes control of the bus by driving the Bus Busy line, negates the request and signals its master that the bus is available.

Some arbiters have a time-out feature, that allows them to withdraw the bus grant if the requesting module does not start using the bus within a prescribed time. This ensures that the bus is not locked up as a transient edge on a request line.

Other arbiters can drive the Bus Clear line when they detect a request with higher priority than that of the module which is currently using the bus, granting the bus to another module.

Utility Bus

The utility bus contains two clock lines, a serial data line, a system reset line, a power fail line, and a system fail line.

The system clock module provides a 16-MHz clock signal (SYSCLK), that is useful for various system functions that require a fixed time reference (for example, for time-outs). This signal is not used for delimiting bus cycles.

For the VMS serial bus, there is a clock signal (SERCLK), which synchronizes operation of the VMS bus. The serial bus can run at 32 Mbit/s, but it can also be run at 16 or 8 Mbit/s. Its protocol is completely independent of the VMEbus.

The power monitor module monitors the status of the power source. When a voltage outside the normal limits is detected, the monitor uses a special line (-ACFAIL) to broadcast a warning to all boards on the bus to prepare for the power shutdown (this is called "graceful shutdown").

When a board detects a system error, it can use the system fail line (-SYSFAIL) to broadcast to the system that its status has changed.

Bus Cycles

The VMEbus specifications define five types of data transfer cycles and two additional types of cycles. The data transfer cycles can be used to transfer 8, 16, or 32 bits of data.

Read and write cycles begin when the master broadcasts an address and an address modifier code, which indicates the type of the bus cycle. Unaligned transfers are possible, for example 4 bytes starting at an odd address.

Block transfer cycles are used to read or write a block of maximum 256 bytes of data. They allow the master to address a single location and then to access that location, as well as the following locations, without providing additional addressing information. When a master initiates such a cycle, the slave latches the address into an address counter, which is incremented subsequently and used for the next transfers.

The maximum length of block transfers is limited to 256 bytes. The reason is to simplify memory board design and to decrease the access time for the memory modules. Without this limitation, a block transfer could begin on one board and switch onto a second board, requiring all memory boards to have the ability to pick up a block transfer in the middle. All memory modules, the one that responds and those that do not, would need to latch the initial address and then increment the address counter on each cycle. Each module would then have to decode the incremented address to see if the address has crossed a board boundary into their own address range. The extra address decoding would increase the access time of the memory module.

By this limitation, if a memory module has a size of at least 256 bytes, and the first address falls within the board's boundaries, all of the rest will also fall in this range. Because only the lower 7 address lines can change during a block transfer, the upper address lines only have to be decoded once, at the beginning of the transfer.

Read-modify-write cycles are used to read from and write to a memory location in an indivisible manner, without permitting any other master to access that location before the end of the operation. This cycle is useful in multiprocessing systems, where certain memory locations are used to provide semaphore functions.

In multiprocessing systems that share resources, a method is needed to allocate these resources, so that a resource being used by one task cannot be used by another at the same time. This cycle is similar to a read cycle, followed by a write cycle, but it does not permit using the bus by another processor between the read and write.

Address-only cycles consist of an address broadcast, without a data transfer. The purpose of this cycle is to allow a master to announce that it is intending to request shortly the contents of a certain address. At a later request, the memory will be able to respond instantly, avoiding the wait states. Thus, two cycles can be overlapped.

Interrupt acknowledge cycles are initiated by interrupt handlers and are used to read status and identification information from an interrupter module.

Bus Arbitration

The VMEbus uses a combination between centralized arbitration and distributed arbitration. There is a single bus arbiter located on the first board, which grants the bus to a request with certain priority level. Within that level, a module will be selected using a daisy-chain scheme.

The VMEbus specifications describe three arbitration algorithms: prioritized, round robin, and single level.

Priority arbitration assigns the bus according to a fixed priority scheme, where each of the four request lines is assigned a priority.

Round robin arbitration assigns the bus on a rotating priority basis. Each of the four request lines is considered equal to the others in priority. If the bus is granted to the requester on bus request line n, then the highest priority is assigned to bus request line n-1, and the lowest to line n. This is also called a fairness arbitration method.

Single-level arbitration only accepts requests on bus request line 3. The daisy-chain connection of that line will ensure that only one requester will use the bus.

Although not described by the VMEbus specifications, other algo­rithms may be used. For example, an algorithm might give highest priority to bus request 3, but use the other levels to grant the bus in a round-robin fashion.

Release of the bus can be accomplished in two ways:

Release When Done RWD

Release On Request ROR

In the first case, the requester module signals the arbiter that it has finished using the bus as soon as its master indicates that it no longer needs the bus. With Release On Request, the requester module does not signal the arbiter unless there is another bus request. To do this, the module must monitor the request lines. This method allows for the imple­mentation of the bus parking procedure.

Micro Channel

In 1987, IBM has launched the PS/2 family of microcomputers. These computers had some improvements, such as: the controller for the VGA adapter and the floppy-disk adapter integrated on the motherboard, new ports for the keyboard and mouse, a higher-performance adapter and interface for the hard disk.

The most important characteristic of these systems was the use of a new extension bus called Micro Channel MCA - Micro Channel Architecture). The PS/2 Model 50Z 55SX and computers are using a 16-bit version of this bus, while the Model 70 and computers are using a 32-bit version.

Although the Micro Channel architecture was primarily developed for the PS/2 family of microcomputers, it was also developed with the capability of being used in IBM's low-end mainframe environments. What follows is a description of the main features of the Micro Channel bus.

Improved Interrupt System

All interrupt signals (IRQ) are level sensitive. Level-sensitive interrupt structures require a simpler logic to implement, are less susceptible to noise interference, and require less software support. These characteristics reduce implementation costs, improve system reliability, and improve perfor­mance. The interrupt control system allows the sharing of an interrupt level, as opposed to the ISA bus, which permits the use of an interrupt level by a single adapter.

High-Performance Transfers

The clock frequency is 10 MHz for the 16-bit version of the bus, and 16 MHz for the 32-bit version. The timing specification defines a default transfer cycle of 200 ns to transfer 4 bytes of data, which corresponds to a transfer rate of 20 MB/s. The specification enables data to be transferred in cycles less than the default.

The actual transfer rate of a system is determined by the maximum transfer rate of the bus master controlling the transfers, and the transfer constraints of the devices attached to the bus (device transfer constraints include transfer rates and transfer widths). The transfer rate with the peripherals can attain 4 MB/s. Disks can transfer data using a streaming procedure, with rates up to 9 MB/s.

32-Bit Address and Data Buses

The 32-bit address bus supports an addressing space of 4 GB of memory or memory-mapped I/O devices. The specification also permits the implementation of a 24-bit subset of this bus. The address bus can also be used as a 16-bit I/O bus.

The 32-bit data bus can also be used as a 24-bit data bus, 16-bit data bus, or an 8-bit data bus. The specification permits a 16-bit subset of the data bus to be implemented when the 24-bit address bus is implemented. The 16-bit data bus can be used to transfer 16 bits or 8 bits of data.

Exception Condition Recovery

An exception condition is defined as any error or status condition that cannot be resolved by typical recovery methods. The exception condition recovery feature permits hardware and software to be implemented that can correct the condition or disable the device creating the exception condition. This feature increases the system's ability to continue functioning.

By exception condition reporting the system error detection overhead will be minimized. Hardware is used to check the integrity of transfer cycles, removing the need for validating transfer cycle integrity from the system and application software. Exception conditions are only reported when they are detected by the hardware support. The error detection and correction code is only executed when it is needed.

Programmable Option Select

The Programmable Option Select (POS) feature eliminates the need for hardware configu­ration switches on the motherboard or expansion boards. It permits device identification, resolves resource assignment conflicts, and provides dynamic system configuration, when supported by appropriate operating system and device driver software.

Programmable option select information is contained in eight 1-byte registers. Each device connected to the bus can be enabled or disabled through a control bit in its POS registers. These registers also contain the device identifier, the exception condition indicator, and optional status information. With this information, the system control software and device drivers can correct exception conditions detected by a device or disable the device.

Arbitration Bus

A 4-bit arbitration bus is specified by the Micro Channel architecture. The purpose of the arbitration system is to support both multitasking and parallel processing. The data bus can be shared by a total of 16 bus masters and slaves. Each bus master is assigned a unique priority level from the lowest priority level F to the highest priority level . The bus master with the priority level F is referred to as the default bus master. It is given control of the bus when there is no other bus master or during an exception condition.

The Micro Channel architecture does not require the default master to be the system master. The system master is the bus master that allocates and administers system resources. The operating system that controls the system resources can be run on any bus master in the system. This allows multiple concurrent operating systems to be run.

A device which wants to use the bus sends its priority level on the arbitration lines. Each device or expansion board monitors the arbitration lines and renounces to the bus if it detects a higher priority request.

Enhancements of the Micro Channel architecture

In 1990 IBM has introduced some enhancements of the Micro Channel bus in order to increase the transfer rate. In the 32-bit or 64-bit streaming transfer mode, address and data transfers occur at every 200 ns, but the next data are transmitted every 100 ns, without transmitting an address before each block of data. Using this procedure, the transfer rate can attain 40 MB/s for a 32-bit bus and a 10-MHz clock. By implementing a 64-bit streaming procedure, data can also be sent on the address bus when it is not busy, the transfer rate attaining 80 MB/s.

The Micro Channel architecture has not been very successful, for several reasons:

the incompatibility with the existing AT or ISA expansion cards;

the performances have not increased significantly compared to the systems with an ISA bus;

higher costs, because of the technology and the licence fees.

However, the Micro Channel architecture has introduced several new concepts which are used at present in the implementation of VL Bus and PCI buses.

EISA

The EISA (Extended Industry Standard Architecture) bus was designed in 1988 by nine IBM competitors. The goal was the extension of the ISA bus (also called the AT bus), to support 32-bit architectures and superior transfer rates, maintaining the compatibility with the existing expansion cards and peripherals. Another goal of the EISA bus design was to compete with IBM's own high-speed bus architecture, the Micro Channel

Many characteristics are similar with those of the Micro Channel architecture, including:

32-bit transfers;

support for multiprocessing;

automatic configuration of the system and expansion cards, without using switches.

The interrupts are edge- or level-triggered, the method used being selected by program. The entire 32-bit address space is fully accessible, not only to the processor, but also to the DMA controllers and bus controllers. Even the 16-bit DMA controllers can have access to the entire address space.

All transfers performed over the EISA bus are synchronized to an 8.33 MHz bus clock signal. The bus supports burst mode transfers, when a transfer is performed in one cycle of the bus clock. This equates to 8.33 million transfers per second. Since the data path is 32-bits wide, a maximum of four bytes may be transferred in one cycle. This equates to a theoretical maximum transfer rate of 33 MB/s.

The principal difference between EISA and Micro Channel is that EISA is backward compatible with the ISA bus, while Micro Channel is not. This means that computers with an EISA bus can use new EISA expansion cards as well as old AT expansion cards. Computers with a Micro Channel bus can use only Micro Channel expansion cards. EISA and Micro Channel are not compatible with each other.

The circuitry used for EISA architectures has a relatively high cost. Because of this disadvantage, the EISA systems have not become widely used architectures, being used especially for network servers.