PCI Bus
PCI Bus Features
Initiator and Target devices
There are two participants in every transfer: the initiator and the target. The initiator, or bus master, is the device that initiates a transfer. The target, or slave, is the device currently addressed by the initiator for performing a data tran 848d31i sfer. All PCI initiator and target devices are referred to as PCI‑compliant agents.
Burst Transfer
A burst transfer consists of a single address phase followed by several data phases. The bus master only has to arbitrate for the bus one time. The start address and transaction type are sent during the address phase. The target device latches the start address into an address counter and will increment the address in each data phase.
With the EISA and Micro Channel buses, the ability to perform burst transfers is established by a negotiation between the bus master and the target device. If either or both of them do not support burst mode transfers, the data block can only be transferred using a series of separate bus transactions. The bus master must arbitrate in order to grant the bus to perform each individual transaction. Another bus master may obtain the bus between two transactions. This can severely limit the transfer rate.
Most PCI data transfers are executed using burst transfers, most devices being designed to support burst mode. If a target device can only handle single transactions, and a bus master attempts to perform a burst transaction, the target terminates the transaction at the end of the first data phase. This forces the master to re‑arbitrate for the bus in order to send the next data item. The target terminates each burst transfer after the first data phase. The performance will be reduced, but single transactions can be used for a device that doesn’t require a high transfer rate.
Assuming that neither the initiator nor the target device inserts wait states in the data phases, a word may be transferred on the rising‑edge of each clock cycle. At a clock frequency of 33 MHz, a transfer rate of 132 MB/s can be achieved in a 32‑bit implementation, or 264 MB/s can be achieved in a 64‑bit implementation. With a bus clock frequency of 66 MHz, 264 MB/s or 528 MB/s transfer rates can be obtained, using 32 or 64‑bit transfers.
Multi-Function Devices
A PCI physical device may take the form of a component integrated onto the system board or the form of an expansion card. Each device may incorporate up to eight separate functions, and such a device is referred to as a multi‑function device.
PCI Bus Clock
The frequency of the clock signal may be from 0 to 33 MHz. The revision 1.0 specification indicated that all devices must support operation from 16 to 33 MHz, recommending support for operation down to 0 MHz. The revisions 2.0 and 2.1 indicate that all PCI devices must support operation within the 0 MHz to 33 MHz range. Support for operation down to 0 MHz provides low‑power and static debug capability. The clock frequency may be changed at any time and may be stopped, but only in the low state.
The revision 2.1 also defines PCI bus operation at speeds of up to 66 MHz.
Address Phase
Every PCI transaction starts with an address phase one clock period in duration. The exception is represented by a transaction using 64‑bit addressing, when the address is supplied in two address phases. During the address phase, the initiator identifies the target device and the type of transaction.
The target device is identified by sending a start address within its assigned range onto the address/data bus. The type of transaction is identified by sending the command type onto the C/BE# (Command/Byte Enable) lines. The initiator asserts the FRAME# signal to indicate the presence of a valid start address and transaction type on the bus. Since the start address is only present on the bus for one clock cycle, every target device must latch the address so that it may subsequently be decoded.
When a target device determines that it is being addressed, it must claim the transaction by asserting DEVSEL# (Device Select). If this signal is not asserted within a predetermined amount of time, the initiator aborts the transaction.
Upon completion of the address phase, the address/data bus is used to transfer data in each of the data phases.
Data Phase(s)
During the data phase or data phases, a data object is transferred between the initiator and the destination. Both initiator and target must indicate that they are ready to complete a data phase by asserting IRDY# (Initiator Ready) and TREADY# (Target Ready). If one or both of these signals are not asserted at the beginning of a clock period, a wait state will be inserted with the duration of a clock period.
Transaction Completion
The initiator identifies the total duration of a transfer with the FRAME# signal. This signal is asserted at the start of the address phase and remains asserted until the initiator is ready (asserts IRDY#) to complete the final data phase.
The initiator indicates that the last data transfer of a burst transfer is in progress by deasserting FRAME# and asserting IRDY#. When the last data transfer has been completed, the initiator returns the PCI bus to the idle state by deasserting the IRDY# signal.
The bus arbitration takes place while a bus master uses the bus. If the bus arbiter had previously granted the bus to another bus master, this master can detect that the bus has returned to the idle state by detecting FRAME# and IRDY# both deasserted.
Configuration Registers
Each functional PCI device have a block of 64 configuration doublewords reserved for the implementation of its configuration registers. The format of the first 16 doublewords is predefined by the PCI specification. This area is referred to as the device’s configuration header. The specification currently defines two header formats, referred to as header type 0 and 1. Header type 1 is defined for PCI-to-PCI bridges, while header type 0 is used for all other devices.
The format of a functional device’s header (other than a PCI-to-PCI bridge) is shown in Figure 1. The registers within this header are used to identify the device, to control its functions, and to detect its status. The usage of the remaining 48 doublewords of configuration space is device‑specific.
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Figure 1. The format of the configuration header. |
Mandatory Registers
These registers must be implemented in every PCI device, including bridges.
Vendor ID Register. This 16‑bit R/O register identifies the manufacturer of the device by a code assigned by an authority that controls the issuance (distribution) of these codes (PCI SIG PCI Special Interest Group). The value FFFFh is reserved and must be returned by the host/PCI bridge when an attempt is made to perform a configuration read from a non‑existent device’s vendor ID configuration register. The read attempt results in a master abort, which is not considered to be an error.
Device ID Register. This 16‑bit value is assigned by the device manufacturer and identifies the type of device.
Command Register. It’s a 16‑bit register, but only bits 9-0 are currently defined, the other bits being reserved for future use. The main functions that can be specified by the contents of this register are described as follows.
I/O Access Enable. When this bit is set to 0, the device is disabled.
Memory Access Enable. When this bit is set to 1, the device responds to PCI memory accesses, if it implements any memory.
Master Enable. When set to 1, enables the device to act as a bus master, if it has bus master capability.
Special Cycle Recognition. When set to 1, the device is enabled to monitor for PCI special cycles. These cycles are used to send messages to target devices, which can monitor the cycles to determine if they are the destinations of the messages.
VGA Palette Snoop Enable. When set to 1, this bit instructs the VGA‑compatible device to perform palette snooping. This option is useful for systems with two display devices: a VGA‑compatible device and another graphics controller. In this case, both devices implement a set of color palette registers at the same I/O addresses. If the processor performs a write to the palette registers, both controllers will recognize the address and assert DEVSEL# and TRDY#, resulting in a collision on these lines.
The configuration software must program one of the devices to actively act as the target, while the other device is programmed to quietly write the data, without asserting DEVSEL# and TRDY#. The VGA device always responds to reads from its color palette registers.
Parity Error Response. When set to 1, the device can report parity errors, otherwise parity errors are ignored.
System Error Enable. When set to 1, the device can assert the SERR# signal, to indicate a system error. All devices that use the SERR# signal must implement this bit. To report parity errors, this bit and the Parity Error Response bit must be set.
After reset, all bits of the command register are cleared to 0, except for a device that must be enabled at startup time because it’s used during the boot process. This disables the device (but it will be accessible for configuration), until it is configured and enabled by the configuration software. Devices that must be accessible at boot time through fixed addresses must implement the I/O Access Enable bit to control the recognition of its fixed address ranges. This would allow the configuration software to disable the recognition of the fixed address ranges after boot up and to reconfigure the address ranges the device responds to.
Status Register. This register keeps the status of PCI bus-related events. The register can be read from, but writes are handled differently than the normal. On a write, bits can be cleared, but not set. A bit is cleared by writing the value 1 to it. This method was selected to simplify the programs. After reading the state and determining the error bits that are set, the programmer clears the bits by writing the value that was read back to the register.
The main information contained in the status register are the following:
66 MHz-Capable. Indicates if the device is capable of running at 66 MHz, or at 33 MHz.
User-Definable Features Supported. The configuration software can detect a device and allocate system resources to it (memory space, I/O space, interrupt line, arbitration priority level, etc.). However, some configurable aspects of certain subsystems cannot be automatically configured when the subsystem is first detected. It is necessary to provide a list of options to be selected by the user. An example would be a network controller card that must be assigned a network node ID. When the subsystem is first installed in the system, the options selected are saved in non‑volatile memory to be used at each startup time.
Data Parity Reported. This bit is only implemented by bus masters and is set in the following conditions: the reporting bus master was the initiator and set the PERR# signal itself or detected it asserted by the target (during a write); and the Parity Error Response bit in the master’s command register is set to 1.
Signaled Target Abort. Set by the target when it terminates a transaction with a target‑abort.
Received Target Abort. This bit is set by a bus master when its transaction is terminated by a target‑abort from the currently-addressed target. All bus masters must implement this bit.
Received Master Abort. This bit is set by a master when its transaction is terminated due to a master‑abort.
Signaled System Error. This bit should be set whenever a device generates a System Error on the SERR# line.
Detected Parity Error. This bit should be set by a device whenever it detects a parity error, even if parity error reporting is disabled.
Revision ID Register. Contains an 8-bit value, set by the manufacturer, which represents the revision number of the device.
Class Code Register. It is a 24-bit register, divided in three fields, which contain: the main class, the subclass, and the programming interface. This register identifies the main function of the device (e.g., a mass-storage controller), a more precise subclass of the device (e.g., an IDE controller), and, in some cases, a programming interface (such as the register set of a VGA controller).
Header Type Register. It is an 8-bit register which defines the format of the configuration header. In addition to the type 0 header, indicated in the figure, a single format is defined, for the bridges between two PCI buses. More formats will be defined in future specifications. Bit 7 of this register indicates whether the device is unifunctional or multifunctional.
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