Pentium Pro Microprocessor

Pentium Pro Microprocessor

General Description

The Pentium Pro microprocessor is the next generation in the Intel 386, Intel 486, and Pentium family of processors. Although, it shares the same name as the fifth-generation Pentium microprocessor, the Pentium Pro is architecturally quite different. Thanks to modern design techniques, including super pipelining, dynam 626f56g ic execution, and on-chip L2 cache, the Pentium Pro can perform at nearly twice the speed of previous Pentium microprocessors. The Pentium Pro processor implements a Dynamic execution micro architecture ----- a unique combination of multiple branch prediction, data flow analysis, and speculative execution while maintaining binary compatibility with the 8086/88, 80286, 80386, 80486, and Pentium processors. The Pentium Pro (code named P6) is a vast improvement over the Pentium, with large changes in the internal architecture (with most of the ideas from the old Pentium thrown out), achieving clock speeds of 150 to 200 MHz.

A significant new feature of the Pentium Pro processor, from a system perspective, is the built-in direct multi-processing support. In order to achieve multi-processing for up to four processors and maintain the memory and I/O bandwidth to support them, new system designs are needed which consider the additional power requirements and signal integrity issues of supporting up to eight loads on a high speed bus.

Since increasing clock frequencies and silicon density can complicate system designs, the Pentium Pro processor integrates several system components which alleviate some of the previous system requirements. The second level cache, cache controller, and Advanced Programmable Interrupt Controller (APIC) are some of the components that existed in previous Intel processor family systems which are integrated into this single component. This integration results in the Pentium Pro processor bus more closely resembling a symmetric multi-processing system bus rather than a previous generation processor-to-cache bus. This added level of integration and improved performance results in higher power consumption and a new bus technology.

The Pentium Pro processor has a decoupled, 12-stage, super pipelined implementation, trading less work per pipe stage for more stages. The Pentium Pro processor also has a pipe stage time 33 percent less than the Pentium processor, which helps achieve a higher clock rate on any given process.

Hardware Specifications

• Available at 150MHz, 166MHz, 180MHz and 200MHz core speeds
• Binary compatible with applications running on previous members of the Intel microprocessor family
• Optimized for 32-bit applications running on advanced 32-bit operating systems
• Dynamic Execution micro architecture
• Single package includes Pentium Pro processor CPU, cache and system bus interface
• Scalable up to four processors and 4 GB memory
• Separate dedicated external system bus, and dedicated internal full-speed cache bus
• 8K/8K separate data and instruction, non-blocking, level one cache
• Available with integrated 256 KB or 512 KB, non-blocking, level two cache on package
• Data integrity and reliability features include ECC, Fault Analysis/Recovery, and Functional Redundancy Checking
• Upgradeable to a future Overdrive® Processor

For the Pentium Pro 200 MHz, some specifications are below:

• 387-pin / ZIF Socket 8
• Superscalar (level 3) Dynamic Execution (0.35 micron)
• External bus 64-bit (pipelined), 66 MHz
• Bus / Core ratio 1/3
• L1 cache 8K code and 8K data (MESI write back protocol)
• L2 cache 512-Kbytes
• Floating point unit 80-bit (pipelined)
• Voltage 3.3 V
• Scalable up to four processors and 4 GB memory

 Architecture

The Pentium Pro used a dynamic execution micro-architecture. It has a three-way superscalar architecture, (executing three instructions per CPU clock) with a pipeline depth of twelve in the multiple execution units (including two for integer operations and one for floating-point operations). It uses dynamic data flow analysis, out-of-order

execution, branch prediction, and speculative execution via register renaming to achieve higher parallelism.

Three instructions decode units work in parallel to each decode object code into smaller operations (micro-ops). These go into an instruction pool, and can be executed out of order by the five parallel execution units (two integer, two FPU and one memory interface unit). The Retirement Unit retires (i.e. writes results to registers and memory) completed micro-ops in their original program order, taking account of any branches.

It has the same two on-chip 8 KB L1 caches as the Pentium (one for instructions, and one for data) which are dual-ported. It also has a 256 KB, 512 KB or 1MB L2 cache supporting up to 4 concurrent accesses, using a dedicated 64-bit (backside) full clock speed bus. The data bus is transaction-oriented, with each access handled as a separate request and response, with numerous requests allowed while awaiting a response. The address bus was expanded to 36 bits, giving a maximum physical address space of 64 GBytes. These parallel features provide a 'non-blocking' architecture further enhance the performance of the processor.

Dynamic Execution Technology

Dynamic Execution Technology can be summarized as optimally adjusting instruction execution by predicting program flow, having the ability to speculatively execute instructions in any order, and then analyzing the program’s dataflow graph to choose the best order to execute the instruction. The implementation of Dynamic Execution of the Pentium Pro processor are shown in the following block diagram including cache and memory interfaces. The 'Units' shown in the diagram represent stages of the Pentium Pro processor pipeline.

• The FETCH/DECODE unit: An in-order unit that takes as input the user program instruction stream from the instruction cache, and decodes them into a series of micro-operations that represent the dataflow of that instruction stream. The pre-fetch is speculative.

• The DISPATCH/EXECUTE unit: An out-of-order unit that accepts the dataflow stream, schedules execution of the micro-operations subject to data dependencies and resource availability and temporarily stores the results of these speculative executions.

• The RETIRE unit: An in-order unit that knows how and when to commit ('retire') the temporary, speculative results to permanent architectural state.
• The BUS INTERFACE unit: A partially ordered unit responsible for connecting the three internal units to the real world. The bus interface unit communicates directly with the L2 (second level) cache supporting up to four concurrent cache accesses. The bus interface unit also controls a transaction bus, with MESI snooping protocol, to system memory.

 Evolution from the Pentium to the Pentium Pro

The Pentium Pro processor succeeds the Pentium line of Intel processors. This processor implements Intel’s dynamic execution micro-architecture, which incorporates a unique combination of multiple branch prediction, data flow analysis, and speculative execution. This enables Pentium Pro processor to deliver higher performance than the Pentium family of processors, while maintaining binary compatibility with all previous Intel architecture processors.