CUPL-to-PEEL* (v2.0)

CUPL-to-PEEL (v2.0)

PEEL-Array Device Fitters

for CUPL 4.5 or greater

Table of Contents

Page

CUPL-to-PEEL Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.1 About CUPL-to-PEEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 About this manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.3 PEEL Array Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.4 Upgrades to CUPL-to-PEEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.0 CUPL-to-PEEL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Using CUPL with PEEL Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3 Minimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.4 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.5 Executing CUPL-to-PEEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.0 CUPL Design Rules for PEEL Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 PEEL Array design rules overview . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 The "Property" statement . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . 8

3.3 Pin and Node Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.4 Dot Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.0 Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Appendix A. Source File Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.0 Introduction

1.1 About CUPL-to-PEEL

CUPL-to-PEEL (v2.0) Device Fitters allow designers to create programming files for ICT's PEEL Array family (PA7024, PA7128, PA7140) using CUPL 4.5 (or greater) high-level design language from Logical Devices. The CUPL development methodology is fully maintained through design entry, compilation and functional simulation. The fitter operates on "Berkeley Espresso" PLA files, that are produced by the CUPL compiler, and creates PEEL Array JEDEC programming files.

CUPL-to-PEEL Device Fitters provide true device independent design entry, therefore, it is not necessary to specify pin numbers, node numbers, global clock, reset or preset nodes. The fitters automatically optimizes the placement of signals on logic cells and I/Os for the best fit. This feature eases the conversion from other PLD designs. A detailed description of the configuration selected by the fitter is stored in a ".log" file.

The fitters also allow use of the PLACE software by optionally creating a ".psf" extension file which allows for architectural viewing of the design in PLACE software. This makes it possible to simulate test vectors stored in the JEDEC file while using the PLACE software. The CUPL-to-PEEL fitters operate on PC compatibles with DOS 3.0 or greater.

1.2 About this Manual

This manual includes operation and reference information for using ICT's CUPL-to-PEEL software (version 2.0). It is meant to be used in conjunction with Logical Devices' CUPL PLD/FPGA Language Compiler. We recommend you first become familiar with CUPL using the CUPL manual before proceeding with CUPL-to-PEEL.

1.3 PEEL-Array Architecture

Programmable Electrically Erasable Logic (PEEL) Arrays are a family of Complex Programmable Logic Devices (CPLDs) based on ICT's CMOS EEPROM technology. PEEL Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and the speed needed for today's programmable logic designs.

The initial PEEL Array family consists of three parts: the PA7024, PA7128 and PA7140, in packages ranging from 24 to 44 pins in plastic DIP, PLCC, and SOIC formats. ICT's CMOS EE technology allows reprogramability and high-speed performance. Wide-gate delays as fast as 9ns for internal (buried) and 15ns external (pin to pin) are possible with PEEL Arrays. Clock frequencies can be as fast as 76.9MHz for sequential functions.

The PEEL Array architecture is based on a versatile multi-level logic array architecture rich in input latches, buried registers and sum-of-product logic functions. The basic logic array structure is similar to that of a PLA (programmable AND, programmable OR) allowing true product term sharing.

PEEL Arrays offer the most flexible logic and I/O cells of any CPLD available today. The unique PEEL Array logic cell incorporates multiple outputs allowing registers and combinational logic to be buried without limiting the use of I/O pins as with other CPLDs. Logic cell registers are user-configurable to be true D, T and JK registers with independent or global clocks, resets, presets, clock polarity and other special features. Additionally, all registers and output enables allow full sum-of-products control.

PEEL Arrays are ideal for implementing a wide variety of general purpose combinational, synchronous and asynchronous logic applications, including: buried counters, complex state-machines, comparitors, decoders, encoders, adders, address/data demux and other wide-gate logic. Because PEEL Arrays allow for multi-level buried logic, designs normally requiring multiple PLDs and/or random logic can be efficiently integrated. For further information on PEEL Arrays please refer to the ICT Data Book.

1.4 Upgrades to CUPL-to-PEEL

Upgrades to CUPL-to-PEEL can be download from the ICT or the Logical Devices bulletin boards.

ICT Inc. BBS:

Modem number: (408) 434-0130

Baud rate: 9600 or lower

Parity: None

Date bit: 8

Stop bit: 1

Logical Devices Inc. BBS:

Modem number: (305) 428-8014

Baud rate: 9600 or lower

Parity: None

Date bit: 8

Stop bit: 1

2.0 CUPL-to-PEEL Operation

2.1 Using CUPL with PEEL Arrays

The steps needed to fit a design: compilation, optimization, simulation and fitter execution, can be carried out in the CUPL menu driven environment. Most of the options associated with this process are selected in CUPL's compile menu, before the design is compiled. The CUPL-to-PEEL fitter operates on the Berkeley Espresso PLA files that are created by the compiler. The following four sections is a description of the steps needed to fit a CUPL design.

2.2 Design Entry

You can use any text editor to create the CUPL source file (extension *.pld). C 959i83j UPL design rules for PEEL Arrays are discussed in detail in section 3 of this manual.

2.3 Minimization

The CUPL compiler operates on the design source file (extension ".pld") and creates a PLA file (extension ".pla") which is in a sum of products format. Logic minimization reduces the number of product terms needed to fit a design. The method used for Logic minimization can be selected from the compiler menu by selecting "<M>inimization Levels". The recommended minimization method is the Espresso reduction.

2.4 Simulation

Test vectors for a design can be entered in a simulation file (extension ".si"). To simulate the test vectors, select "<S>imulate after compilation" in the compilation menu. After the fitter has created the Jedec file, test vectors can be appended to the Jedec by going to the CUPL main menu and selecting "<S>imulate CUPL File". CUPL then prompts for the name of the simulation file and then displays a "CSIM Simulator" menu. To append test vectors to the Jedec file, select "<JEDEC> download format" from this menu. For this process to be possible, all pin numbers must be specified in the source file. The fitter assigned pin numbers can be included in the source file, by using CUPL's BACKPIN.EXE utility. (This utility is executed from the DOS prompt).

2.5 Executing CUPL-to-PEEL

To execute the fitter within the CUPL environment, select "<C>ompile" from the main menu and then "<JEDEC> download format" in the compile sub-menu. The CUPL-to-PEEL fitter program will then be executed after the designed is compiled, optimized and simulated.

Execution of the fitter results in a JEDEC file which can be used to program a device and a detailed log file which includes the pin and node numbers assigned by the fitter, the equations assigned to each LCC sum-term and the configuration of the LCCs and global cells. A pin placement file (extension *.plc) is also created which can be used with the CUPL's BACKPIN.EXE utility to put the fitted pin and node numbers in the source file.

The commands for executing the fitters from the DOS prompt are the following:

ICT7024 [-i] pla_filename [options]

ICT7128 [-i] pla_filename [options]

ICT7140 [-i] pla_filename [options]

Where pla_filename is a OPEN-ABEL input file created by the compiler. Fitter options can also be specified in the source file by using the "ARGS" property statement (see section 3.2). The following is a list of the fitter options:

-dev device_name

Where "device_name" can be F7024, F7024C, F7128, F7140 or F7140C. Device names which have C as their last character (e.g. F7140C) are for PLCC packages, otherwise they are DIP packages. The purpose of using the -dev flag is to specify the type of package for the target device.

-log log_filename

where log_filename is the name to be assigned to the log file. If this option is not used, the log file name defaults to the base of pla_filename with extension .log.

ignore

The pin and node numbers in the source file are ignored. This option is useful when the source file is written for a different device. Whether a successful fit is possible depends on the design and the architecture of the device it was written for.

psf

The fitter creates a PLACE Source File (PSF). This allows for architectural viewing of the design in the PLACE software. It also allows for the simulation of the test vectors stored in the JEDEC file using the PLACE wave form simulator.

msg

As explained in section 3.3 (node specification for global cells), the fitter examines all feasible configurations of global cell signals, to select the one which is optimum. If the msg flag is include on the command line, the fitter creates a message file (extension ".msg") which includes all the error messages (if any) and the number of used product terms for each configuration of global signals the fitter examines. The error messages included in the ".msg" file are usually more specific than those included in the ".log" file and the msg option should be used if some problems are encountered when fitting a design.

3.0 CUPL Design Rules for PEEL Arrays

The extensive design capability of PEEL Arrays is primarily due to their architecture which is unique amongst standard PLDs. The designer is offered a host of options in placing signals, selecting the polarity of signals and utilizing multiple global cells. As a result of all these options, the manual placement of signals for a large design can become a complex job. CUPL-to-PEEL is a design automation tool which can automatically fit device independent designs on PEEL Arrays. It is designed to find the configuration of signals which is optimum in terms of the number of product terms and the number of logic cells used.

Alternatively, if you wish to specify partially or fully the implementation of your design, you can do so by using pin and node numbering, global cell declaration and using the property statement. These issues are discussed in the next four sections.

3.1 PEEL Array design rules overview

To fit a CUPL design on a particular device, the name of the device can be declared in the header section of the source file with CUPL's Device statement. Alternatively, the device can be selected in CUPL's main menu by selecting the <D>evice item in the menu. (Please refer to CUPL documentation.) The device names used for PEEL-Arrays are:

DIP PLCC

PA7024 F7024 F7024LCC

PA7128 F7128 F7128 (same pin out for PLCC and DIP)

PA7140 F7140 F7140LCC

For example, to fit a design contained in module COUNTER on PA7024, the following line can be included in the header section of COUNTER.PLD:

3.2 The "Property" Statement.

The property statement is used in CUPL to pass to the fitter the type of device specific information which can not be specified with the usual CUPL format. With the CUPL-to-PEEL fitter, the property statement has various applications. These are distinguished by the first word appearing inside on the property statement line. This word can be one of the following (lower case can also be used):

LCC_CLOCK, CLOCK_NOT_GLOBAL, DT, TD, DJK, JKD, FLAGS (All PEEL devices)

PRELOAD_A, PRELOAD_B, UNLOAD_A, UNLOAD_B (PA7140 only)

LCC_CLOCK

Clock pins can be fully specified by numbering during declaration. As an alternative, the property statement can be used to declare clock pins. The following format is used:

PROPERTY device_name ;

where "device_name" can be ICT7024, ICT7128, ICT7140 or ICT_PA. (The last one can be used with all PEEL-Arrays). "clock_pin" is the name of the pin which is to be assigned as one of the two dedicated clock pins. "clock_pin" must be declared separately with the usual CUPL syntax for declaring pins. If the pin number of "clock_pin" is specified when it is declared, it can only take one of the two possible values corresponding to the clock pin numbers for PEEL Arrays. The following numbers can be used for clock pins:

PA7024 (DIP): 1, 13

PA7024 (PLCC): 2, 16

PA7128: 1, 28

PA7140 (DIP): 1, 21

PA7140 (PLCC): 2, 24

If the pin number of "clock_pin" is not specified, the fitter will automatically assign to it a valid pin number.

The LCC_CLOCK property statement can be used twice. For example:

The application of the LCC_CLOCK property statement is optional. Even if clock pins are not specified by numbering or by the property statement, the fitter will automatically assign a clock pin. (Please refer to section 3.3 for an explanation of automatic pin assignments.)

CLOCK_NOT_GLOBAL

This application of the property statement is to specify those registered pins and nodes which can not directly use the global clock. For these pins and nodes the clock signal will be routed through the array. The following format is used:

PROPERTY device_name ;

where "device_name" can be ICT7024, ICT7128, ICT7140 or ICT_PA. (The last one can be used with all PEEL-Arrays). For pins and nodes whose name appear after CLOCK_NOT_GLOBAL, the clock signal will be routed through the array, even if their clock signal is the same as the global clock.

CLOCK_NOT_GLOBAL example:

DT, TD, DJK, JKD

These applications of the property statement are used to identify those pins and nodes which use register type control. The following format is used:

PROPERTY device_name ;

where "device_name" can be ICT7024, ICT7128, ICT7140 or ICT_PA. (The last one can be used with all PEEL-Arrays). "register_type" can be one of the following:

DT (D-type register dynamically changed to T-type register)

DJK (D-type register dynamically changed to JK-type register)

TD (T-type register dynamically changed to D-type register)

JKD (JK-type register dynamically changed to D-type register)

For the pins and nodes whose name appear after "register_type", an extension .ffm global signal must be defined. (Please refer to section 3.3, Node specification for global cell control functions.) When this global signal becomes high, it changes the register type of the pins and nodes listed on the property statement.

Register type control example:

PRELOAD_A, PRELOAD_B, UNLOAD_A, UNLOAD_B

These applications of the property statement are only applicable for PA7140. For PA7140 it is possible to use a low voltage signal at a pin to preload or unload the register on the connected Logic Control Cell (LCC). The low voltage preload operation should be contrasted with high voltage preload which can be used only during programming.

On the A and B global cells, signals are dedicated to preload and unload low voltage operations. These signals can be sum of products and in the CUPL language they are declared as global nodes. When a global preload signal goes high and a LCC register is clocked, the signal on the pin connected to the register is preloaded into the register. When a global unload signal goes high and a LCC register is clocked, the content of the register is unloaded to the connected pin.

PRELOAD_A, PRELOAD_B, UNLOAD_A and UNLOAD_B applications of the property statement are used to specify preload and unload nodes for group A and group B global cells. The following format is used:

PROPERTY ICT7140 ;

where "global_node_type" can be PRELOAD_A, PRELOAD_B, UNLOAD_A or UNLOAD_B. "node_name" is the name of the node to be placed on the global cell.

Preload example:

The example file precnt.pld (Appendix A., Example 8) gives a demonstration of how to implement a low voltage preloadable counterdynamic register type.

The low voltage preload and unload functions are not supported by the CUPL simulator.

FLAGS

The FLAGS property statement is used as an alternative method to pass to the fitter the "psf", "ignore" and "msg" command line options listed in section 3.5. The following format is used:

PROPERTY device_name ;

"device_name" can be ICT7024, ICT7128, ICT7140 or ICT_PA. (The last one can be used with all PEEL-Arrays). For example to create a PSF file, the following line can be placed in the source file:

3.3 Pin and Node Assignments

For true device independent design entry the actual pin and node numbers need not be specified. CUPL-to-PEEL will optimally place pins and nodes to minimize the number of logic cells and product terms used. The ".log" file created by the fitter includes all the pin and node numbers assigned by the designer or the fitter, the equations assigned to each LCC sum-term and the configuration of the LCCs and global cells.

If you wish to specify the pin and node numbers, the following design rules should be used.

Node Assignments for buried Logic Control Cell (LCC) outputs

Each Logic Control Cell (LCC) feed back signal must be identified by a node. If you wish to specify the actual node number for each LCC you must do following:

for PA7024 and PA7128: add 30 to the connected pin number.

for PA7140: add 50 to the connected pin number.

PA7024 and PA7128 example:

PA7140 example:

Node Assignments for input cell (IOC and INC) latches/registers

When Input/Output Cell (IOC) or Input Cell (INC) registers are to be used, each must be identified by a node. If you wish to specify the actual node number for each IOC you must do the following:

for PA7024 and PA7128: add 60 to the connected pin number.

for PA7140: add 100 to the connected pin number.

PA7024 and PA7128 example:

PA7140 example:

Node Specification for Global Cells

The purpose of declaring a global node is to force a signal to be placed on a global cell. Global nodes should not be declared with node numbers.

The following is an example of declaring global nodes:

Alternatively, if some global signals are left unspecified by the designer, CUPL-to-PEEL calculates the number of product terms needed to fit the design for every feasible configuration of the global signals. A selection is made based on which configuration results in the smallest number of used product terms. Hence, if you prefer the fitter to optimally select global signals, you should not use global node declarations.

Example of global signal selection by the fitter: 

3.4 Dot Extensions

Dot extensions allow proper specification of how an equation is to be applied to the device architecture. Dot extensions recognized by CUPL-to-PEEL are listed as follows:

.ck  Clock input to an edge triggered input register

.le Enable input to latch

.oe  Output enable

.d Data input to a D-type register

.t  Data input to a T-type register

.j  Data input to J of a JK-type register

.k Data input to K of a JK-type register

.ap or .pr Asynchronous preset (independent or global)

.ar or .re Asynchronous reset (independent or global)

.ffb  Register-type control from global cell

.io  Feedback from pin

example:

4.0 Error Messages

The following is an alphabetically ordered list of the error messages placed by CUPL-to-PEEL in the ".log" file or the ".msg" file. The error messages included in the ".msg" file are for each configuration of global signals the fitter examines, hence they do not necessarily correspond to the final configuration selected by the fitter.

Can not allocate fixed_products.

Not enough system memory available for fitter operation.

Can not open JEDEC file: "jedec_file_name".

A possible reason is that "jedec_file_name" is an invalid file name.

Can not open pla file: "pla_file_name".

Possible reasons are that "pla_file_name" is an invalid file name or it is not accessible in the directory the fitter is executed.

Can not open PSF file: "psf_file_name".

A possible reason is that "psf_file_name" is an invalid file name.

Global clock "node_name" must use a single product term.

The expression for IOC or INC global clocks can not be a sum.

Global register type "node_name" must use a single product term.

The expression for global register type control signals can not be a sum.

Global register type "pin_name" must use a single product term.

The expression for global register type control signals can not be a sum.

INC "node_name"

All INCs must use the same clock.

All Input Cell clock signals must use the same expression.

INC "node_name"

INC clock must use a single product term.

The expression for the Input Cell clock signal can not be a sum.

INC "node_name" is of an incorrect type.

The fitter uses the dot extensions defined for a node to determine its type. If the extensions are inconsistent with the architecture of the particular PEEL Array, the "incorrect type" error message is generated. For example, it is incorrect to define a latch enable signal and a preset signal for the same node. Check the source file to see the dot extensions defined for "node_name" and compare these with the extensions available for Input Cells.

IOC "node_name"

All group A IOCs must use the same clock.

(PA7024 and PA7140 only) All group A IO Cell clock signals must have the same equation.

IOC "node_name"

All group B IOCs must use the same clock.

(PA7024 and PA7140 only) All group B IO Cell clock signals must have the same equation.

IOC "node_name"

All IOCs must use the same clock.

(PA7128 only) All IO Cell clock signals must have the same equation.

IOC "node_name"

Incorrect node number.

If node numbers are provided, they have to follow the numbering scheme described in section 3.3 of this manual.

IOC "node_name"

IOC clock must use a single product term.

The expression for an IO Cell clock signal can not be a sum.

IOC "node_name" is of an incorrect type.

The fitter uses the dot extensions defined for a node to determine its type. If the extensions are inconsistent with the architecture of the particular PEEL Array, the "incorrect node type" error message is generated. For example, it is incorrect to define a latch enable signal and a preset signal for the same node. Check the source file to see the dot extensions defined for "node_name" and compare these with the extensions available for Input/Output Cells.

IOC "node_name"

Number of product terms needed exceeds the maximum.

(PA7140 only) The number of product terms used by "node_name" is greater than the maximum of 60. Higher levels of logic reduction (e.g. group reduction) or changing the polarity of some equations associated with "node_name" may solve this problem.

LCC clock does not appear in the pin field.

The name declared using the LCC_CLOCK property must be declared separately as a pin.

LCC "node_name" is of an incorrect type.

The fitter uses the dot extensions defined for a node to determine its type. If the extensions are inconsistent with the architecture of the particular PEEL Array, the "incorrect type" error message is generated. For example, it is incorrect to define a latch enable signal and a preset signal for the same node. Check the source file to see the dot extensions defined for "node_name" and compare these with the extensions available for Logic Control Cell signals.

LCC "node_name"

Number of product terms needed exceeds the maximum.

(PA7140 only) The number of product terms used by "lcc_name" is greater than the maximum of 60. Higher levels of logic reduction (e.g. group reduction) or changing the polarity of some equations may solve this problem.

Log filename is invalid.

The name appearing after -log on the command line is not a valid file name.

No fit could be found.

This error message is generated when the design can not be fitted on the device. The message file (extension ".msg") should be examined to find the specific reason no fit could be found. The message file is generated if the fitter is executed from the command line with flag msg (section 2.5).

Node "node_name"

All group A nodes must use the same global register control.

(PA7024 and PA7140) All group A register control signal must use the same expression.

Node "node_name"

All group B nodes must use the same global register control.

(PA7024 and PA7140) All group B register control signal must use the same expression.

Node "node_name"

All nodes must use the same global register control.

(PA7128 only) All register control signal must use the same expression.

Node "node_name"

Can not invert polarity.

The equation for certain signal types (e.g. extension .T, .J, .K, .AP, .AR, .OE, etc. signals) must have positive polarity (no invert sign "!" on the left hand side of the equation).

Node "node_name" can not use global register type control.

The fitter has determined that the "node_name" is not a Logic Control Cell node and therefore can not use global register type control.

Node "node_name.extension"

Extension is not valid for input field.

Review section 3.4 for a list of extensions available for PEEL Arrays.

Node "node_name"

Incorrect node number.

If node numbers are provided, they have to follow the numbering scheme described in section 3.3.

Node "node_name" is of an incorrect type.

The fitter uses the dot extensions defined for a node to determine its type. If the extensions are inconsistent with the architecture of the particular PEEL Array, the "incorrect node type" error message is generated. For example, it is incorrect to define a latch enable signal and a preset signal for the same node. Check the source file to see the dot extensions defined for "node_name" and compare these with the extensions available for buried nodes on PEEL-Arrays.

Node "node_name"

Preset must be global with JK-type register.

Independent preset signals and extension ".k" signals both use the sum_b input to Logic Control Cells, hence they are mutually exclusive for the same node (Please refer to the architecture of Logic Control Cells).

Not enough memory to create INS.

Not enough system memory available for fitter operation.

Not enough memory to create OUTS.

Not enough system memory available for fitter operation.

Not enough memory to create array.

Not enough system memory available for fitter operation.

Number of group A LCCs needed is greater than 10.

(PA7024 only) Too many pins or nodes are placed on group A or the design is too large for the device.

Number of group A LCCs needed is greater than 12.

(PA7140 only) Too many pins or nodes are placed on group A or the design is too large for the device.

Number of group B LCCs needed is greater than 10.

(PA7024 only) Too many pins or nodes are placed on group B or the design is too large for the device.

Number of group B LCCs needed is greater than 12.

(PA7140 only) Too many pins or nodes are placed on group B or the design is too large for the device.

Number of INCs needed is more than 12.

(PA7128 and PA7140 only) The number of Input Cells need to fit the design is more than the maximum 12.

Number of LCCs needed is greater than 12.

(PA7128) The number of Logic Control Cells need to fit the design is more than the maximum 12.

Number of LCCs needed is greater than 20.

(PA7024) The number of Logic Control Cells need to fit the design is more than the maximum 20.

Number of LCCs needed is greater than 24.

(PA7140) The number of Logic Control Cells need to fit the design is more than the maximum 24.

Number of product terms needed exceeds the maximum.

Higher levels of logic reduction (e.g. group reduction) or using other polarity options (e.g. optimizing with auto-polarity) may solve this problem.

Only one INC and two IOC clocks allowed.

(PA7024 and PA7140 only) This error message is generated if more than one Input Cell clock or more than two Input/Output Cell clocks are defined.

Only one IOC clock and one INC clock allowed.

(PA7128 only) This error message is generated if more than one Input Cell clock or more than one Input/Output Cell clock are defined.

Only one global INC clock allowed.

More than one Input Cell clock global node has been declared.

Only one global IOC and one global INC clock allowed.

(PA7128 only) More than one IO Cell clock global node or more than one Input Cell clock global node has been declared.

Only one global LCC clock can be declared.

(PA7128 only) More than one global LCC clock has been declared using the LCC_CLOCK property statement.

Only one global register type signals allowed.

(PA7128 only) This error message is generated if more than one register control global signal is declared.

Only pins 1 and 13 can be used as global clocks.

(PA7024 only) The pin number of the pin declared using the LCC_CLOCK property statement must be 1 or 13.

Only pins 1 and 28 can be used as global clocks.

(PA7128 only) The number of the pin declared using the LCC_CLOCK property statement must be 1 or 28.

Only pins 2 and 24 can be used as global clocks.

(PA7140 only) The number of the pin declared using the LCC_CLOCK property statement must be 2 or 24.

Only two IOC clocks allowed.

(PA7024 and PA7140 only) This error message is generated if more than two IOC global nodes are declared.

Only two IOC clocks and one INC clock allowed.

(PA7024 and PA7140 only) This error message is generated if more than two IOC global nodes or more than one Input Cell clock have been declared.

Only two global LCC clocks can be declared.

(PA7024 and PA7140 only) More than two global LCC clocks have been declared using the LCC_CLOCK property statement.

Only two global register type signals allowed.

(PA7024 and PA7140 only) This error message is generated if more than two register control global nodes are declared.

Pin and node do not fit.

Signals defined for "pin_name" and "lcc_name" conflict.

Pin "pin_name"

All group A pins must use the same global register control.

(PA7024 and PA7140 only) This error message is generated if more than one register control signal is defined for group A.

Pin "pin_name"

All group B pins must use the same global register control.

(PA7024 and PA7140 only) This error message is generated if more than one register control signal is defined for group B.

Pin "pin_name"

All pins must use the same global register control.

(PA7128 only) This error message is generated if more than one register control signal is defined.

Pin "pin_name"

Can not invert polarity.

The equation for certain signal types (e.g. extension .T, .J, .K, .AP, .AR, .OE, etc. signals) must have positive polarity (no invert sign "!" on the left hand side of the equation).

Pin "pin_name", IOC "ioc_name"

Pin and node do not fit.

Possible reasons are:

- "ioc_name" is an input register but its input is not from "pin_name"

- "ioc_name" is a sum_d internal feedback node and "pin_name" is output enabled.

Pin "pin_name" is of an incorrect type.

The fitter uses the dot extensions defined for a pin to determine its type. If the extensions are inconsistent with the architecture of the particular PEEL Array, the "incorrect type" error message is generated. For example, it is incorrect to define a ".d" signal for an input pin. Check the source file to see the dot extensions defined for "pin_name" and compare these with extensions which are valid for the particular type of pin.

Pin "pin_name", Node "ioc_name"

Pin and node do not fit.

Possible reasons could be:

- "ioc_name" is an input register but its input is not from "pin_name"

- "ioc_name" is a sum_d internal feedback node and "pin_name" is output enabled.

Pin "pin_name", Node "lcc_name"

Attempting to put two registers on the same cell.

This error message is generated if pin and node numbers imply that a registered pin and a registered node must be placed on the same Logic Control Cell. Only a single registered signal can be placed on a Logic Control Cell.

Pin "pin_name", Node "lcc_name"

Clock conflicts with reset and output enable.

This error message is generated when the clock and the reset signals are both independent (not global) and the pin is output enabled.

Pin "pin_name"

Number of product terms needed exceeds the maximum.

(PA7140 only) The number of product terms used by "pin_name" is greater than the maximum of 60. Higher levels of logic reduction (e.g. group reduction) or changing the polarity of some equations associated with "pin_name" may solve this problem.

Pin "pin_name"

Reset must be global with JK-type register.

Independent preset signals and extension ".k" signals both use the sum_b input to Logic Control Cells, hence they are mutually exclusive for the same node (Please refer to the architecture of Logic Control Cells).

PLA file name must be provided.

The name of the PLA file is not provided on the command line.

Reading output: "output.extension"

Extension is not valid for output field.

This error message is generated when a signal which appears on the left hand side of an equation has an incorrect extension.

Reading pla file: only type f and fr accepted.

The PLA files supported by the fitters can only of type f or fr.

Reading pla file: property is of an incorrect format.

The property statement is not of the format supported by CUPL-to-PEEL.

Too many global presets.

The number of global preset signals defined is more than the maximum available for the device. The maximum number is:

2 for PA7024

1 for PA7128

2 for PA7140

Too many global resets.

The number of global reset signals defined is more than the maximum available for the device. The maximum number is:

2 for PA7024

1 for PA7128

2 for PA7140

Too many group A IO cells.

(PA7024 and PA7140 only) Too many pins or IO nodes are placed on group A.

Too many group B IO cells.

(PA7024 and PA7140 only) Too many pins or IO nodes are placed on group B.

Too many Input Cells.

Number of nodes or pins which have to be placed on Input Cells is too large.

Too many input pins.

The number of pins declared is more than the number of available pins on the device.

Too many IO Cells.

Number of nodes or pins which have to be placed on IO Cells is too large.

Too many nodes.

The number of nodes declared is more than the number of available nodes on the device.

Too many pins.

The number of pins declared is more than the number of available pins on the device.

Too many product terms.

The number of product terms needed to fit the design is more than the maximum available for the device. Higher levels of logic reduction (e.g. group reduction) or changing the polarity of some equations may solve this problem.

Appendix A. Source File Examples

The following is a list of source file examples which are included in the following pages

of this manual. Designs 1-7 are of a tutorial nature and should be reviewed for a better understanding of the design process using CUPL-to-PEEL.

File name demonstrates . . . Page

glbpre.pld global preset node declaration 27

glbclk.pld Input/Output Cell clock declaration 28

ioc_reg.pld Input/Output Cell declaration 30

inc_reg.pld Input Cell declaration 31

cnt8.pld counter implementation 33

states.pld state machine with decode 35

fdback.pld the meaning of various feed-back dot extensions 36

precnt.pld low voltage preloadable counter 42

wave2.pld processor interface and wave form generation 42

10. mult4.pld 4-bit multiplier 42

The following designs are also distributed with CUPL-to-PEEL: cntr7024.pld, gate7024.pld, jack7024.pld, port7024.pld, regs7024.pld.

Example 1.

Source file: glbpre.pld

/* Source file example for CUPL-to-PEEL Device Fitter (version 2.0)

Date: 2-17-1994 */

Name glbpre;

Partno PA;

Date 2/17/94;

Revision 01;

Designer SA;

Company ICT;

Assembly None;

Location None;

Device F7128;

/* This example demonstrates global preset node declarations.

The procedure for global reset declaration is identical. */

/* input pins */

pin = preset_1;

pin = preset_2;

pin = clock;

pin = data;

/* registered pins */

pin = Q0;

pin = Q1;

/* global node */

pinnode = global_preset_node;

This global node will be used to place the preset signal for

Q0 on a global cell. For Q1 we will not declare a global node.

However, the fitter may automatically place the preset signal

for Q1 on a global cell, provided that this action is possible

and it leads to a reduction in the number of product terms.

Unless you want to force a signal to be placed on a global cell,

it is a good idea not to declare global nodes and let the fitter

make the decision. */

[Q0, Q1].ck = clock;

[Q0, Q1].d = data;

global_preset_node = preset_1; /* The preset signal on global cell

will be preset_1. */

Q0.ap = global_preset_node;

Q1.ap = preset_2; /* No global cell defined, but the fitter

can place preset_2 on a global cell anyway. */

Simulation file: glbpre.si

Name glbpre;

Partno PA;

Date 2/17/94;

Revision 01;

Designer SA;

Company ICT;

Assembly None;

Location None;

Device F7128;

order: clock, %2, data, %2, preset_1, %2, preset_2, %4, Q0, %2, Q1;

vectors:

C 0 1 1 H H /* both registers are preset */

C 0 0 0 L L

Example 2.

Source file: glbclk.pld

/* Source file example for CUPL-to-PEEL Device Fitter (version 2.0)

Date: 2-17-1994 */

Name glbclk;

Partno PA;

Date 2/17/94;

Revision 01;

Designer SA;

Company ICT;

Assembly None;

Location None;

Device F7140;

/* input pins */

pin = latch;

pin = enable_1;

pin = enable_2;

pin = enable_3;

pin = in_1;

pin = in_2;

pin = in_3;

/* output pins */

pin = out_1;

pin = out_2;

pin = out_3;

/* input nodes */

pinnode = node_1;

pinnode = node_2;

pinnode = node_3;

/* global clock nodes */

pinnode global_clock_node_1;

pinnode global_clock_node_2;

/* node_1, node_2, node_3 will be placed on Input or IO cells */

node_1.l = in_1;

node_2.l = in_2;

node_3.l = in_3;

/* Definning global clock nodes.

The nodes will be placed by the fitter on global cells. */

global_clock_node_1 = latch & enable_1;

global_clock_node_2 = latch & enable_2;

/* Defining clocks for each cell: */

node_1.le = global_clock_node_1;

node_2.le = global_clock_node_2;

/* As the following equation demonstrates, it is not necessary to

use gloabl node declarations to assign clock signals for IOCs or INCs. */

node_3.le = latch & enable_3;

out_1 = node_1;

out_2 = node_2;

out_3 = node_3;

Simulation file: glbclk.si

Name glbclk;

Partno PA;

Date 2/17/94;

Revision 01;

Designer SA;

Company ICT;

Assembly None;

Location None;

Device F7140;

order: in_1, %2, in_2, %2, in_3, %2,

enable_1, %2, enable_2, %2, enable_3, %2, latch, %4,

out_1, %2, out_2, %2, out_3;

vectors:

1 1 1 0 0 0 C * * * /* All three latches disabled */

1 1 1 1 0 0 C H * * /* node_1 enabled */

1 1 1 0 1 0 C H H * /* node_2 enabled */

1 1 1 0 0 1 C H H H /* node_3 enabled */

1 1 1 0 0 0 C H H H /* All three latches disabled */

0 0 0 0 0 0 C H H H /* Changing input data */

0 0 0 1 1 1 C L L L /* node_1 and node_2 and node_3 enabled */

Example 3.

Source file: ioc_reg.pld

/* Source file example for CUPL-to-PEEL Device Fitter (version 2.0)

Date: 2-17-1994 */

Name ioc_reg;

Partno PA;

Date 2/17/94;

Revision 01;

Designer SA;

Company ICT;

Assembly None;

Location None;

Device F7024;

This design demonstrates node declarations for IO Cells.

It fits on PA7024, PA4128 or PA7140. */

/* Input pins */

pin = clock;

pin = in_1;

pin = en;

/* Output pins */

pin = io_pin;

pin = out_pin;

/* IOC node declarations */

pinnode = ioc_node;

/* equations */

io_pin = in_1;

io_pin.oe = en;

ioc_node.le = clock;

ioc_node.l = io_pin.io; /* input to ioc_node is from io_pin */

out_pin = ioc_node; /* output of ioc_node is fed back thru the array

to out_pin */

Simulation file: ioc_reg.si

Name ioc_reg;

Partno PA;

Date 2/17/94;

Revision 01;

Designer SA;

Company ICT;

Assembly None;

Location None;

Device F7024;

order: in_1, %2, clock, %2, en, %4, io_pin, %2, out_pin;

vectors:

0 C 1 L L

1 0 1 H L

1 C 1 H H

0 0 1 L H

X C 0 0 L

X 0 0 1 L

X C 0 1 H

X 0 0 0 H

Example 4.

Source file: inc_reg.pld

/* Source file example for CUPL-to-PEEL Device Fitter (version 2.0)

Date: 2-17-1994 */

Name inc_reg;

Partno PA;

Date 2/17/94;

Revision 01;

Designer SA;

Company ICT;

Assembly None;

Location None;

Device F7128;

This design demonstrates node declarations for INC Cells.

It fits on PA4128 or PA7140. */

/* Input pins */

pin = clock;

pin = in_1;

/* Output pin */

pin = out_pin;

/* INC node declarations */

pinnode = inc_node;

/* equations */

inc_node.le = clock;

inc_node.l = in_1; /* input to inc_node from input pin */

out_pin = inc_node; /* output of inc_node is fed back thru the array

to out_pin */

Simulation file: inc_reg.si

Name inc_reg;

Partno PA;

Date 2/17/94;

Revision 01;

Designer SA;

Company ICT;

Assembly None;

Location None;

Device F7128;

order: in_1, %2, clock, %4, out_pin;

vectors:

0 C L

1 0 L

1 C H

0 0 H

Example 5.

Source file: cnt8.pld

/* Source file example for CUPL-to-PEEL Device Fitter (version 2.0)

Date: 2-17-1994 */

Name cnt8;

Partno PA;

Date 2/17/94;

Revision 01;

Designer SA;

Company ICT;

Assembly None;

Location None;

Device F7128;

/* This design implements an 8-bit counter. When the count reaches 255,

carry is set to 1. The design fits on PA7024, PA7128 or PA7140. */

pin = clock;

pin = reset;

pin = carry;

/* declare 8 pins to be used as counter output */

$REPEAT i = [0..7]

pin = Q;

$REPEND

field count = [Q7..0];

/* equations */

count.ck = clock;

count.ar = reset;

/* up counter: */

Q0.t = 'b'1;

Q1.t = Q0;

Q2.t = Q0 & Q1;

Q3.t = Q0 & Q1 & Q2;

Q4.t = Q0 & Q1 & Q2 & Q3;

Q5.t = Q0 & Q1 & Q2 & Q3 & Q4;

Q6.t = Q0 & Q1 & Q2 & Q3 & Q4 & Q5;

Q7.t = Q0 & Q1 & Q2 & Q3 & Q4 & Q5 & Q6;

carry = count:'h'FF;

Simulation file: cnt8.si

Name cnt8;

Partno PA;

Date 2/17/94;

Revision 01;

Designer SA;

Company ICT;

Assembly None;

Location None;

base: decimal;

order: reset, %2, clock, %4, count, %2, carry;

vectors:

1 C "0" L

$for i = 1..255 :

$set reset = 0;

$set clock = C;

$comp count = count + 1;

$if count="254" :

$set carry = H;

$else :

$set carry = L;

$endif;

$out;

$endf;

Example 6.

Source file: states.pld

/* Source file example for CUPL-to-PEEL Device Fitter (version 2.0)

Date: 2-17-1994 */

Name states;

Partno PA;

Date 2/17/94;

Revision 01;

Designer SA;

Company ICT;

Assembly None;

Location None;

Device F7128;

This design is an example of a state machine. The output from the

registers implementing the state machine are decoded before being

fed to the ouput pins. The design fits on PA7024, PA7128 or PA7140. */

pin = CLK;

/* Input pins */

pin = I0;

pin = I1;

pin = I2;

field I = [I2..0];

/* Output pins */

pin = O0;

pin = O1;

pin = O2;

pin = O3;

field O = [O3..O0];

/* Registers to implement state machine S */

pinnode = S0;

pinnode = S1;

field S = [S1, S0];

sequence S

/* equations */

S.ck = CLK;

O = S:'h'0 & ['b'0, 'b'0, 'b'0, 'b'0];

append O = S:'h'1 & ['b'0, 'b'1, 'b'1, 'b'0];

append O = S:'h'2 & ['b'1, 'b'0, 'b'0, 'b'0];

append O = S:'h'3 & ['b'0, 'b'1, 'b'0, 'b'0];

Simulation file: states.si

/* Source file example for CUPL-to-PEEL Device Fitter (version 2.0)

Date: 2-17-1994 */

Name states;

Partno PA;

Date 2/17/94;

Revision 01;

Designer SA;

Company ICT;

Assembly None;

Location None;

Device F7128;

order: CLK, %2, I, %4, O;

vectors:

C '0' "0"

C '1' "6"

C '2' "4"

C '2' "0"

Example 7.

Source file: fdback.pld

/* Source file example for CUPL-to-PEEL Device Fitter (version 2.0)

Date: 2-17-1994 */

Name fdback;

Partno PA;

Date 2/17/94;

Revision 01;

Designer SA;

Company ICT;

Assembly None;

Location None;

Device F7140;

/* This design demonstrates the effect of various feed back signals

for an inverted pin. */

pin = !Q;

pin = P1;

pin = P2;

pin = P3;

pin = clock;

Q.d = P1;

Q.ck = clock;

P2 = Q; /* feedback from register */

P3 = Q.io; /* feedback from pin */

Simulation file: fdback.si

Name fdback;

Partno PA;

Date 2/17/94;

Revision 01;

Designer SA;

Company ICT;

Assembly None;

Location None;

Device F7140;

Order: clock, %2, P1, %4, P2, %2, P3;

Vectors:

C 0 L H

C 1 H L

Example 8.

Source file: precnt.pld

/* Source file example for CUPL-to-PEEL Device Fitter (version 2.0)

Date: 2-17-1994 */

Name cnt8;

Partno PA;

Date 2/17/94;

Revision 01;

Designer Joe Peel;

Company ICT;

Assembly None;

Location None;

Device F7128;

This design implements a low voltage preloadable counter on PA7140.

Note that since the CUPL simulator does not support low voltage preload,

the test vectors would not pass the CUPL simulation. However they would

pass programmer functional simulation and PLACE simulation. */

/* registers to implement counter */

$repeat i = [0..7]

pin = Q;

$repend

pin = clock;

pin = preload_pin;

pinnode = preload_node;

/* Preload property statements: */

property ict7140 ;

property ict7140 ;

prelaod_node is declared as the global preload signal

for group A and group B cells. */

field count = [Q7..Q0];

preload_node = preload_pin; /* Definning the global preload signal.

When preload_pin goes high, preload

is activated. */

count.ck = clock;

Q0.t = 'b'1;

Q1.t = Q0;

Q2.t = Q0 & Q1;

Q3.t = Q0 & Q1 & Q2;

Q4.t = Q0 & Q1 & Q2 & Q3;

Q5.t = Q0 & Q1 & Q2 & Q3 & Q4;

Q6.t = Q0 & Q1 & Q2 & Q3 & Q4 & Q5;

Q7.t = Q0 & Q1 & Q2 & Q3 & Q4 & Q5 & Q6;

Example 9.

Source file: wave2.pld

/* Source file example for CUPL-to-PEEL Device Fitter (version 2.0)

Date: 2-17-1994 */

Name wave2;

Partno PA;

Date 2/17/94;

Revision 01;

Designer SA;

Company ICT;

Assembly None;

Location None;

Device F7140;

This design consists of:

12-bit registered counter (registers Q0 to Q11),

microprocessor interface,

8-bit input latch (registers N0 to N7),

8-bit comparitor,

input synchronization latches (latches i1 and i2),

waveform decode logic.

The processor interface allows a start count value to be written

to the upper 8-bits of the counter and a final "last" value to the

latch. The counter starts counting when the "last" latch is written to

and stops when the count reaches last. The output waveform (W0..W4) is

generated by decoding the state of the counter.

The design can be fitted on PA7024 and PA7140 */

/* Input pins */

pin = clock;

pin = WR;

pin = CS;

pin = A0;

pin = in1;

pin = in2;

pinnode = i1;

pinnode = i2;

$repeat i = [0..7]

pin = D;

$repend

field data = [D7..0];

$repeat i = [0..7]

pinnode = N;

$repend

field last = [N7..0];

pin = !done;

pinnode = load;

/* Output pins */

$repeat i = [0..3]

pin = W;

$repend

$repeat i = [0..11]

pinnode = Q;

$repend

/* defenitions */

field count = [Q11..0];

field lower_cnt = [Q1..0];

field upper_bits = [Q11..4];

field lower_bits = [Q3..0];

last = data;

last.le = !WR & !CS; /* When WR is high and A0 is high, write to counter */

load = !WR & !CS & A0; /* When WR is high and A0 is low, write to last. */

count.ck = clock;

upper_bits.t = load & (last $ upper_bits);

lower_bits.t = load & lower_bits;

append count.t = !load & !done & ('h'1

# 'h'2 & Q0

# 'h'4 & [Q0..1]:&

# 'h'8 & [Q0..2]:&

# 'h'10 & [Q0..3]:&

# 'h'20 & [Q0..4]:&

# 'h'40 & [Q0..5]:&

# 'h'80 & [Q0..6]:&

# 'h'100 & [Q0..7]:&

# 'h'200 & [Q0..8]:&

# 'h'400 & [Q0..9]:&

# 'h'800 & [Q0..10]:&

# 'h'1000 & [Q0..11]:&);

!done = ((Q4 & !N0) # (!Q4 & N0) /* done = (upper_bits == last) */

# (Q5 & !N1) # (!Q5 & N1)

# (Q6 & !N2) # (!Q6 & N2)

# (Q7 & !N3) # (!Q7 & N3)

# (Q8 & !N4) # (!Q8 & N4)

# (Q9 & !N5) # (!Q9 & N5)

# (Q10 & !N6) # (!Q10 & N6)

# (Q11 & !N7) # (!Q11 & N7));

[i1, i2].le = clock;

[i1, i2] = [in1, in2]; /* Latched inputs in1 and in2. */

append [W0, W1, W2, W3] = count:['d'0..'d'1023] & ['b'1, 'b'1, i1, Q0];

append [W0, W1, W2, W3]

= count:['d'1024..'d'1535] & lower_cnt:'h'0 & ['b'1, 'b'1, 'b'1, Q0];

append [W0, W1, W2, W3]

= count:['d'1024..'d'1535] & lower_cnt:'h'1 & ['b'0, 'b'1, i1, Q0];

append [W0, W1, W2, W3]

= count:['d'1024..'d'1535] & lower_cnt:'h'2 & ['b'0, 'b'0, 'b'1, Q0];

append [W0, W1, W2, W3]

= count:['d'1024..'d'1535] & lower_cnt:'h'3 & ['b'1, 'b'0, i2, Q0];

append [W0, W1, W2, W3]

= count:['d'1536..'d'4095] & !Q0 & ['b'1, 'b'0, i1, Q1];

append [W0, W1, W2, W3]

= count:['d'1536..'d'4095] & Q0 & ['b'1, 'b'1, i2, Q1];

Simulation file: wave2.si

Name wave2;

Partno PA;

Date 2/17/94;

Revision 01;

Designer SA;

Company ICT;

Assembly None;

Location None;

Device F7024;

base: hex;

order: clock, %1, WR, %1, CS, %1, A0, %1, data, %1, in1, %1, in2,

%4, W0, %1, W1, %1, W2, %1, W3, %1, count, %1, last;

vectors:

C X 1 X 'X' 0 0 * * * * "*" "*"

C 1 0 1 '01' 0 0 * * * * "*" "*"

C 0 0 1 '01' 0 0 * * * * "*" "01"

/* writing data to count */

C X 1 X '01' 0 0 H H L L "010" "01"

C 1 0 0 '02' 1 0 H H H L "010" "01"

C 0 0 0 '02' 1 0 H H H H "011" "02"

/* writing data to last and starting count */

C X 1 X '02' 0 0 H H L L "012" "02"

C X 1 X 'X' 0 0 H H L H "013" "02"

C X 1 X 'X' 0 0 H H L L "014" "02"

C X 1 X 'X' 0 0 H H L H "015" "02"

C X 1 X 'X' 0 0 H H L L "016" "02"

C X 1 X 'X' 0 0 H H L H "017" "02"

C X 1 X 'X' 0 0 H H L L "018" "02"

C X 1 X 'X' 0 0 H H L H "019" "02"

C X 1 X 'X' 0 0 H H L L "01A" "02"

C X 1 X 'X' 0 0 H H L H "01B" "02"

C X 1 X 'X' 0 0 H H L L "01C" "02"

C X 1 X 'X' 0 0 H H L H "01D" "02"

C X 1 X 'X' 0 0 H H L L "01E" "02"

C X 1 X 'X' 0 0 H H L H "01F" "02"

C X 1 X 'X' 0 0 H H L L "020" "02"

/* counting until upper_bits == last */

/* count stoped */

C X 1 X 'X' 0 0 H H L L "020" "02"

C X 1 X 'X' 0 0 H H L L "020" "02"

C X 1 X 'X' 0 0 H H L L "020" "02"

Example 10.

Source file: mult4.pld

/* Source file example for CUPL-to-PEEL Device Fitter (version 2.0)

Date: 2-17-1994 */

Name mult4;

Partno PA;

Date 2/17/94;

Revision 01;

Designer SA;

Company ICT;

Assembly None;

Location None;

Device F7140LCC;

This module implements a 4-bit registered multiplier on a PA7140.

It takes five clock cycles to generate the result. The design consists of

a state machine (implemented by node m0), a counter (implemented by T-type

registers t0 and t1) and adders (implemented by the functions adder_slice

and carry_out). The inputs are latched so that they are free when the

result is not ready. Similarly, the outputs are disabled when the result

is not ready.

function adder_slice(A,B,Cin)

function carry_out(A,B,Cin)

pin = start;

pin = clock;

pinnode = m0; /* To implement state diagram mode */

field mode = [m0];

$define idle 'b'0

$define multiply 'b'1

pin = done; /* When finished done goes high */

$repeat i = [0..3]

pin = ai; /* Inputs for the first 4-bit number */

pinnode = a; /* Input latches */

pin = bi; /* Inputs for the second 4-bit number */

pinnode = b; /* Input latches */

$repend

field A = [a3..a0];

field Ai = [ai3..ai0];

field B = [b3..b0];

field Bi = [bi3..bi0];

$define c0 'b'0 /* The first carry in is always zero */

pinnode = c1;

pinnode = c2;

pinnode = c3; /* Combinational carry for the adders */

$repeat i = [0..7]

pin = r; /* Registered result output */

$repend

field result = [r7..r0];

pin = t0;

pin = t1; /* To implement the counters */

field count = [t1, t0];

sequence mode

count.t = mode:idle & start & count # /* zero the counter */

mode:multiply & !(t1 & t0) & ('b'01 # 'b'10 & t0);

/* count up */

done.d = mode:idle & !start & done # /* done remains unchanged */

mode:multiply & count:'h'3; /* set done = 1 */

At each count, A is shifted and added to the result, provided that the

corresponding bit on B is 1. */

/* no shift and add to result */

$repeat i = [0..3]

append r.d = count:'h'0 & b0 & a & m0;

$repend

/* shift one and add to result */

$repeat i = [0..2]

append r.d = count:'h'1

& (b1 & adder_slice(r, a, c) # !b1 & r) & m0;

append c = count:'h'1 & b1 & carry_out(r, a, c);

$repend

append r4.d = count:'h'1

& (b1 & adder_slice(r4, a3, c3) # !b1 & r4) & m0;

append r5.d = count:'h'1 & b1 & carry_out(r4, a3, c3) & m0;

append r0.d = count:'h'1 & r0;

/* shift two and add to result */

$repeat i = [0..2]

append r.d = count:'h'2

& (b2 & adder_slice(r, a, c) # !b2 & r) & m0;

append c = count:'h'2 & b2 & carry_out(r, a, c);

$repend

append r5.d = count:'h'2

& (b2 & adder_slice(r5, a3, c3) # !b2 & r5) & m0;

append r6.d = count:'h'2 & b2 & carry_out(r5, a3, c3) & m0;

append [r0..r1].d = count:'h'2 & [r0..r1];

/* shift three and add to result */

$repeat i = [0..2]

append r.d = count:'h'3

& (b3 & adder_slice(r, a, c) # !b3 & r) & m0;

append c = count:'h'3 & b3 & carry_out(r, a, c);

$repend

append r6.d = count:'h'3

& (b3 & adder_slice(r6, a3, c3) # !b3 & r6) & m0;

append r7.d = count:'h'3 & b3 & carry_out(r6, a3, c3) & m0;

append [r0..r2].d = count:'h'3 & [r0..r2];

append result.d = result & !m0; /* hold result when in idle mode */

A = Ai; /* Latches are used to free inputs */

B = Bi; /* when result is not ready */

[A, B].le = start & clock;

[result, count, done, mode].ck = clock;

result.oe = done; /* Output disabled until done goes high */

Name mult4;

Partno PA;

Date 2/17/94;

Revision 01;

Designer SA;

Company ICT;

Assembly None;

Location None;

Device F7140;

order: start, %2, clock, %2, Ai, %2, Bi,

%4, result, %2, done, %2, count, %2, mode, %2, A, %2, B;

vectors:

set Ai = '0';

$for i = 0..7 :

set Bi = '1';

$for j = 0..7 :

$comp A = Ai;

$comp B = Bi;

set start = '1';

set clock = C;

set result = ZZZZZZZZ;

$set done = *;

$set count = "0";

$set mode = H;

$out;

$set start = '0';

$set clock = C;

$set result = ZZZZZZZZ;

$set done = L;

$set count = "1";

$set mode = H;

$out;

$set start = '0';

$set clock = C;

$set result = ZZZZZZZZ;

$set done = L;

$set count = "2";

$set mode = H;

$out;

$set start = '0';

$set clock = C;

$set result = ZZZZZZZZ;

$set done = L;

$set count = "3";

$set mode = H;

$out;

$set start = '0';

$set clock = C;

$comp result = Ai * Bi;

$set done = H;

$set count = "3";

$set mode = L;

$out;

$set start = '0';

$set clock = C;

$comp result = Ai * Bi;

$set done = H;

$set count = "3";

$set mode = L;

$out;

$comp Bi = Bi + 2;

$endf;

$comp Ai = Ai + 2;

$endf;