MOSFET Current Sources

MOSFET Current Sources

With the evolution of integrated circuits, it was necessary to reduce the number of resistors in the circuit, and the solution was the transistor current source. An added bonus was that the circuit was generally greatly improved as well. Here, the b 14314n135o asic principle is introduced, followed by a discussion of the standard method of increasing the current output resistance with source degeneration. The application of a current-source configuration for balancing a differential amplifier stage is discussed.

9.1 Basic Current Source

An example of a current source based on PMOS transistors is shown here in Fig. 9.1. It consists of the reference circuit, consisting of transistor M₃ and bias resistor R_bias. The reference-circuit transistor is diode connected. The induced V_SG3 = V_SD3 is applied to the current-source transistor M₂. Thus, the drain current, or current-source current of M₂ is the mirror of the reference current. In an integrated circuit, any number of current sources can be referenced to the reference current or voltage. Current ratios are implemented with the selection of the relative gate widths of the transistors.

Figure 9.1. PMOS current source. The current set up by the reference circuit of M₃ and R_bias is mirrored as the current of M₂.

The design of the reference circuit is based on a dc solution to the reference current, I_D3. The solution is obtained from the loop equation

Equation 9.1

and transistor equation

Equation 9.2

The current in M₂ is

Equation 9.3

where

and

W₂ and W₃ are the transistor gate widths of M₂ and M₃, respectively, and L is the channel length. In general, the ratio of currents is

Equation 9.4

where the approximation can often be used for simplicity with long-channel devices. This avoids the necessity of knowing the source - drain voltages. The signal output resistance at the drain of M₂ is

Equation 9.5

In the project of the current source, we will scan V_SD2 and compare the source current with the reference current.

9.2 Current Source with Source Degeneration

It is normally desirable to have the output resistance of a current source as large as possible. It can be improved over the circuit of Fig. 9.1 by adding resistance in the source branch, as shown in Fig. 9.2, to establish source degeneration (negative feedback). In the discussion of the signal circuit, it is necessary to represent the diode-connected transistor with its linear equivalent, which is just a resistance of magnitude, 1/g_m. This can be seen by inspection of the circuit of Fig. 9.3. The voltage, V_d, is applied directly to the gate such that V_gs = V_d and the drain current is I_d = g_mV_d. Thus the resistance of the diode is just V_d/I_d = 1/g_m. The result is the same for the PMOS and NMOS as is always true for signal linear models.

Figure 9.2. Current-source circuit with source resistors to improve output resistance at drain of current-source transistor, M₂.

Figure 9.3. Signal circuit for diode-connected NMOS.

The new output resistance at the drain of M₂ for the current-source circuit with source resistors (Fig. 9.2) can be derived based on the signal circuits shown in Fig. 9.4. The output resistance is defined as R_o = V_o/I_o, where I_o is the drain current flowing in conjunction with the application of the test voltage V_o. Figure 9.4(b) replaces M₃ with the signal model equivalent and M₂ with the ideal, intrinsic transistor model (current source) along with output resistance,1/g_ds2. The transistor symbol represents the ideal transistor with output current g_m2V_sg2, positive in the direction shown.

Figure 9.4. (a) Signal circuit of Fig. 9.2. (b) Reference transistor circuit replaced with the linear model. The effective resistance at the gate of the current source transistor plays no role other than to return the gate to ground since I_g2 = 0.

The current I_o flowing through the transistor and up through the resistor, R_S2, develops a voltage across the resistor, V_RS2 = I_oR_S2. Since I_g2 = 0, an input circuit loop equation is simply V_gs2 = -I_dR_S2. The transistor linear-model current source, g_m2V_gs2, thus is down, as shown in the signal-circuit diagram of Fig. 9.4(b). The sum of currents through 1/g_ds is

Equation 9.6

The voltage V_o is thus

Equation 9.7

and the output resistance is

Equation 9.8

This magnitude can be assessed with the use of ( ), which is g_m = 2I_D/ V_effp. Eliminating g_m in (9.8) results in

Equation 9.9

If the magnitude of the voltage across R_S2 is several volts, then R_o is much greater than 1/g_ds2, since V_eff2 is typically a fraction of a volt. In integrated circuits, R_S may be replaced with an additional current source, in which case the expression becomes

Equation 9.10

where the output resistance of the added current source is approximately 1/I_D2l_p

9.3 Differential Amplifier Balancing Circuit

The principle of the balancing of the differential-amplifier stage (e.g., in an opamp) is often based on a circuit similar to that in Fig. 9.2, as shown in Fig. 9.5. Imbalance could be due, for example, to V_tpo1 V_tpo2 and k_p1 k_p2. Balancing is implemented by adjusting R₁ R₂, where R₁ = R_S1//R_x and R₂ = R_S2||R_y.

Figure 9.5. Balancing circuit. Voltage V_D2 is controlled by selecting the relative values of R_x and R_y.

The relationship among the currents, parameters, and resistors is obtained by writing the loop equation around the source resistors and the gate - source terminals, which is

Equation 9.11

A solution for V_SD2 can be obtained from ( ) for a given set of parameters, resistors, and bias variables; on the other hand, R_x and R_y are adjusted to obtain a certain V_SD2.

For the special case of I_D1 = I_D2 = I_D, the difference between the resistors in ( ) is

Equation 9.12

For a numerical example, suppose the goal is to set By design, in (9.12),

Equation 9.13

Any slight possible difference in l_p is neglected.

In a practical opamp with this balancing configuration, the source nodes are connected to external pins. These pins are connected through external resistors R_x and R_y to V_DD as shown in Fig. 9.5. For adequate adjustment sensitivity, R_x and R_y are greater than R_S1 R_S2 by at least a factor of 10. In practice, the external resistances are implemented with a potentiometer.

Assume that the transistor parameter values are V_tpo1 = 1.49 V, V_tpo2 = 1.51 V, k_p1 = 345 mA/V², k_p2 = 335 mA/V², and l_p = 0.02 V^-1. Also assume that the bias current I_D = 100 mA. We select R_S1 = R_S2 = R_S = 3 kW (Voltage I_DR_s = 0.3 V) and we use R_x + R_y = R_pot = 25 kW; the two resistors are segments of a 25-kW potentiometer. The segments of the potentiometer are then determined from a solution to

Equation 9.14

where dR is obtained from ( ) with V_SD2 = V_SG1 as obtained from ( ). The resistor values are R_x = 16 kW and R_y = 9 kW to give R₁ = 2.53 kW and R₂ = 2.25 kW

An evaluation of V_SD2 without the balancing circuit can be made by setting dR = 0 in ( ) and for solving V_SD2 to obtain

Equation 9.15

V_SG1 is again obtained from (

With the numbers from the example above, V_SD2 = 7.87 V. We note that with l_p = 0.01 V^-1, the solution is V_SD2 = 13.2 V and the circuit might well have exceeded the power-supply limits. If V_tpo1 = 1.45 V, V_tpo2 = 1.55 V, and lp = 0.02 V^-1 that is, for an extreme case of the difference of threshold voltage, the balancing circuit will still function but now R_x = 21.8 kW and R_y = 3.24 kW with a small R₂ = 1.56 kW

9.4 Summary of Equations