PMOS Common-Source Amplifier Stage with Current-Source Biasing

CD4007 Pin Diagram

(NMOS)

DC drain current - voltage relation (PMOS).

Midfrequency gain versus 13413h79n I_D.

Midfrequency gain versus I_D with bypass capacitor C_s.

Gate signal voltage, V_g, frequency-dependent relation to signal source, V_s.

Gain frequency response with C_s only (C_g infinite).

Approximate f_3dB with C_g infinite.

Components

V_SG versus I_D from Lab Projects 4,5.

LabVIEW Computations

Procedure

Install your value of R_S in the Front Panel. Verify that VDD = 10V. Run DC.vi to verify your selection of R_S R_D. Goal is I_D mA. Verify that VG is about VDD/2. Default and save the Front Panel. Note that VSD is about 2VSG.

LabVIEW Computations

Use Project06.mcd for calculations.

SubVI's

FG1Chan.vi

SpecAnaly.vi

LabVIEW Computation

Procedure

The SubVI of Gain.vi, FG1Chan.vi, sends out a signal with sine-wave peak Vs (Chan1_out). The first measurement is with only capacitor C_g installed. Be sure to conform to the capacitor polarity requirement. Set the Signal Frequency to 1000 Hz. Set your value of RS and check VDD = 10 V. Run Gain.vi to measure the gain. The gain should be less than 1 without the source bypass capacitor. A signal of Vs 0.5 V should thus suffice for good linearity and measurement precision.

Now install the capacitor C_s. Note that the source is at a positive voltage. Run the VI while setting Vs at various values. Adjust Vs until the THD% (total harmonic distortion, %) is reduced to below about 5%.

Continue to lower Vs and run Gain.vi. Verify that the measured gain, av, is invariant for smaller values of Vs except as eventually limited by DAQ resolution and noise. Find the largest Vs (up to 5% THD), which is consistent with a constant gain measurement with increasing Vs.

Run the VI again with a lower frequency (e.g., 800 Hz) to verify that the gain is not frequency dependent in this frequency range. Now default and save the Front Panel.

Procedure

The frequency of the input source voltage is swept from 1 to 1000 Hz to 1000 Hz. Set Vs in FreqResp.vi as determined above for a valid voltage gain measurement. Open FG1Chan.vi to observe the waveform at the output.

Set your value of RS. Run FreqResp.vi without C_s. Recall that the gain will be less than 1. The frequency response is dictated by C_g only. Verify that f_3dB is about equal to or less than 1 Hz. Note that f_3dB <1 H if the digital indicator f3dB indicates 1 Hz.

Install C_s and run the VI. Obtain a value for f3dB. Default and save the Front Panel. Then use XYtoDataFile.vi to obtain a data file for the frequency response. A copy of the VI is in Project06.llb.