Poarta logica NU de tip 7404
Fisierul de intrare nu.cir
Poarta NU 7404
VCC 3 0 5V
X 1 2 7404
.LIB DC3EVAL.LIB
V 1 0 PWL(0s 0V 1.5s 0V 1.5001s 5V 1.7s 5V 1.7001s
0V 3.5s 0V 3.5001s 5V 4.5s 5V 4.5001s 0V 5s 0V)
R 3 2 100K
.TRAN 0.01ms 5s
.PROBE
.END
Poarta logica SI
Fisierul de intrare si.cir
Poarta SI
VCC 6 0 5V
X1 1 3 7404
X2 2 4 7404
X3 3 4 5 7402
.LIB DC3EVAL.LIB
V1 1 0 PWL(0s 0V 0.1ms 5v 1s 5V 1.0001s 0V 2s 0V
2.0001s 5V 3s 5V 3.0001s 0V 4s 0V 4.0001 5V 5s 5V)
V2 2 0 PWL(0s 0V 1.5s 0V 1.5001s 5V 1.7s 5V 1.7001s
0V 3.5s 0V 3.5001s 5V 4.5s 5V 4.5001s 0V 5s 0V)
R1 6 3 100K
R2 6 4 100K
R3 6 5 100K
.TRAN 0.01ms 5s
.PROBE
.END
Poarta logica SAU
Fisierul de intrare sau.cir
Poarta SAU
VCC 5 0 5V
X1 1 2 3 7402
X2 3 4 7404
.LIB DC3EVAL.LIB
V1 1 0 PWL(0s 0V 0.1ms 5v 1s 5V 1.0001s 0V 2s 0V
2.0001s 5V 3s 5V 3.0001s 0V 4s 0V 4.0001 5V 5s 5V)
V2 2 0 PWL(0s 0V 1.5s 0V 1.5001s 5V 1.7s 5V 1.7001s
0V 3.5s 0V 3.5001s 5V 4.5s 5V 4.5001s 0V 5s 0V)
R1 5 3 100K
R2 5 4 100K
.TRAN 0.01ms 5s
.PROBE
.END
Poarta logica SI-NU
Fisierul de intrare si-nu.cir
Poarta SI-NU
VCC 7 0 5V
X1 1 3 7404
X2 2 4 7404
X3 3 4 5 7402
X4 5 6 7404
.LIB DC3EVAL.LIB
V1 1 0 PWL(0s 0V 0.1ms 5v 1s 5V 1.0001s 0V 2s 0V
2.0001s 5V 3s 5V 3.0001s 0V 4s 0V 4.0001 5V 5s 5V)
V2 2 0 PWL(0s 0V 1.5s 0V 1.5001s 5V 1.7s 5V 1.7001s
0V 3.5s 0V 3.5001s 5V 4.5s 5V 4.5001s 0V 5s 0V)
R 7 6 100K
.TRAN 0.01ms 5s
.PROBE
.END
Poarta logica SAU-NU
Fisierul de intrare sau-nu.cir
Poarta SAU-NU 7402
.LIB DC3EVAL.LIB
VCC 4 0 5V
R 4 3 100K
X 1 2 3 7402
V1 1 0 PWL(0s 0V 0.1ms 5v 1s 5V 1.0001s 0V 2s 0V
2.0001s 5V 3s 5V 3.0001s 0V 4s 0V 4.0001 5V 5s 5V)
V2 2 0 PWL(0s 0V 1.5s 0V 1.5001s 5V 1.7s 5V 1.7001s
0V 3.5s 0V 3.5001s 5V 4.5s 5V 4.5001s 0V 5s 0V)
.TRAN 0.01ms 5s
.PROBE
.END
|
