RDS DEMODULATOR + FILTRU

TDA 30B

RDS DEMODULATOR+FILTRU

INALTA PERFORMANTA, FILTRU BANDA57KHz  

ARI (INDICATIE SK) SI IESIRE SEMNAL RDS DE CALITATE

OSCILATOR 4 MHz SAU

MHzOPTIONAL

ZGOMOT REDUSMIXAT BIPOLAR/TEHNOLOGIE CMOS

DESCRIERE

TDA 7330 B este un demodulator RDS care capteaza informatia RDS transmisa de statiile radio FM. Iesirea semnalului de date RDDA si de clock RDCL poate fi procesata de un decodor RDS (microprocessor).

Microprocesorul opereaza conform normelor EBU (EUROPEAN BROADCASTING UNION) si include 2 intrari de filtru de 57kHz, un detector de trecere, un clock, bucla PLL 57kHz, decoder bifazic PSK, decoder diferential, indicator ARI si semnal de iesire RDS de calitate.

DIAGRAMA BLOC

DIP20 SO20

ORDERINGNUMBERS:

TDA7330B TDA 330BD

TDA73 0B

NIVELE MAXIME ABSOLUTE

DATE TERMICE

^{PINCONNECTION} Topview

DESCRIERE PINI

TDA7 30B

^{ELECTRICALCHARACTERISTICS(V}CC ^{V,Tamb= C;Rg W;fosc= MHz V}IN ^{mVrmsunlessotherwisespecified)}

SUPPLY

FILTER measuredanpin4FILOUT

CROSS DETECTOR

OSCILLATOR

*)FSEL pinhas an internal KWpulldownresistor A MHz QUARTZmust beused *) A MHz QUARTZmust beused.

DEMODULATOR

Note(

Thephasenonlinearityis defined as:DPh=|-2 ff ff ff

whereffxistheinput-output phasedifferenceatthefrequencyfx x=

TDA73 0B

^{ELECTRICALCHARACTERISTICS}(continued)

^Note( The thharmonic KHz) must be lessthan 40dBinrespectto the inputsignal KHz plus gain.

^{Figure :}RDS timingdiagram

OUTPUT TIMING

The generated 5Hz   output clock  RDCL line)issynchronizedtotheincomingdata. According to the internal PLL lock condition this

Figure :TestCircuit

data change can resultson the falling oron the

risingclockedge.

Whicheverclockedgeisusedby thedecoder ris

ingorfalling edge)thedatawillremainvalidfor

^msecaftertheclock transition.

TDA7 30B

APLICATII

A good  DC  decoupling between V_CC   ^and

GROUND isnecessary: a 100nF ceramicca-

pacitor,withlowresistanceandlowinductance athighfrequency,directlyconnectedonpin

^(V_CC^{)and5(GND)isrecommended.}

Asmall seriesinductance ( mH) or resistor

W)maybeusedforsupplylinefiltering.

The Layout pathpin2-C2-pin5must beas

shortas possible.

If thesupplyline,afterthepoweronhasasoft and disturbed (spikes) slope, a capacitor  of

^{100nF between  POR and VCC,  is  racom} mended.

Thevarioustestingpinshavenosenseforthe customer

Figure :P C.boardandcomponentlayoutoffig.3 1scale)

TDA73 0B

  ^Figura Gainvs.Frequency  ^{Figura :}GroupDelayvs.Frequency

TDA7 30B

DIM